1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device which operates in synchronism with a clock supplied from the outside of the device.
2. Description of the Related Art
Nowadays, the CPUs operate at high speeds, and it is thus required that semiconductor devices such as DRAMs (Dynamic Random Access Memories) input and output data signals at increased bit rates in order to increase the data transmission rate. Examples of such memory devices are an SDRAM (Synchronous Dynamic Random Access Memory) and an FCRAM (Fast Cycle Random Access Memory), which memories operate in synchronism with an external clock and achieve high-speed operation.
A description will now be given of an operation of the FCRAM with reference to FIG. 1. It will be noted that the SDRAM has the same circuit configuration as shown in FIG. 1.
FIG. 1 shows a circuit configuration of the periphery of a memory cell of the FCRAM. The circuit shown in FIG. 1 includes a capacitor 501, NMOS (N-channel Metal Oxide Semiconductor) transistors 502-512, a PMOS (P-channel MOS) transistor 513, PMOS transistors 521 and 522, and NMOS transistors 523 and 524. The PMOS transistors 521 and 522 and the NMOS transistors 523 and 524 form a sense amplifier 520.
The capacitor 501 of the memory cell is capable of storing one-bit information. When a sub-word line selecting signal SW is enabled, the NMOS transistor 502 which serves as a cell gate is turned on, and the data stored in the capacitor 501 is read out to a bit line BL. At that time, a bit line transfer signal BLT1 is at a high level, and the NMOS transistors 503 and 504 are thus in the conducting states. On the other hand, a bit line transfer signal BLT0 is at a low level, and the NMOS transistors 505 and 506 are thus in the non-conducting states.
Thus, data on bit lines BL and /BL is read by the sense amplifier 520 via the NMOS transistors 503 and 504. The data sensed and held by the sense amplifier 520 is read out to a pair of data bus lines DB and /DB via the NMOS transistors 510 and 511 which serve as column gates, when a column line select signal CL is enabled.
A data write operation is implemented by the sequence reverse to that of the above-mentioned data read operation, so that data on the pair of data bus lines DB and /DB is stored in the capacitor 501.
FIG. 2 is a timing chart of the data read operation of the FCRAM having the circuit shown in FIG. 1. A description will now be given, with reference to FIGS. 1 and 2, of a data read timing in a case where the burst length of read data is equal to 4 (BL=4).
When an activation command (ACT) is applied to the FCRAM, the FCRAM internally generates a signal RASZ which instructs data stored in the memory cells 201 to be sensed by the sense amplifiers 220. Then, the FCRAM generates, at appropriate timings, word line select signals MW and SW, the bit line transfer signals BLT and sense amplifier drive signals SA1 and SA2. Thus, the data in the memory cells 201 appear on the bit lines BL and are then sensed and amplified by the sense amplifiers 220.
Further, the FCRAM generates an internal precharge signal PRE when a given time elapses after receiving the signal RASZ.
In response to receipt of a read command RD, the column line select signals CL of the columns selected by the column address become high, and the data held in the sense amplifiers 220 are read to the data bus lines DB and /DB. The data thus read are 4-bit parallel data, which are converted into serial data. The serial data is output to the outside of the FCRAM as read data DQ.
When the above data read operation is repeatedly performed with the burst length BL equal to 4, consecutive read data having no discontinuity is obtained as shown in FIG. 2 because the read cycle of the random access is short.
When the read operation or the write operation is repeatedly performed in the conventional FCRAM, data can be read or written efficiently. However, the read operation and the write operation are alternately performed, data cannot be read or written efficiently, as compared to the successive read or write operations.
The above problem will be described with reference to FIG. 3, which is a timing chart of a sequence in which the read and write operations are alternately performed.
When the read operation is performed as shown in part (A) of FIG. 3, it takes a certain time to obtain a read data output (Q) after the read command R is received. Generally, a read data latency is defined as the number of clock cycles which exist in the interval between the read command and the read data output. Similarly, a write data latency is defined as the number of clock cycles which exist in the interval between the write command and an associated write data input.
Conventionally, write data is simultaneously input together with the write command. Hence, the write data latency is equal to "0". Thus, as shown in part (A) of FIG. 3, the write command W subsequent to the preceding read command R is required to be input after the read data output Q resulting from the above preceding read command R is completed. Thus, the case shown in part (A) of FIG. 3 needs an interval equal to 9 clocks from the read command R to the write command W.
Further, as shown in part (A) of FIG. 3, the read command R following the write command W is required to be input after write data associated with the above write command W is completely stored in the memory cells. Thus, the case shown in part (A) of FIG. 3 needs an interval equal to 6 clocks from the write command W to the read command R.
It can be seen from the above description that the case shown in part (A) of FIG. 3 needs a read-write cycle equal to 15 clocks.
Next, a description will be described, with reference to part (B) of FIG. 3, of a case where the read data latency and the write data latency are equal to each other. In the case shown in part (B) of FIG. 3, it is possible to reduce the interval between the read command R and the write command W to the minimum tolerance time (lRC) between the read command R and the write command W defined in the general inter-bank formation. This is because the read data latency and the write data latency are equal to each other, and the inputting of write data associated with the write command W is executed after the outputting of read data associated with the read command R is completed.
However, in order to input the read command R after the write command W is inputted, it is necessary to store write data associated with the above write command are stored in the memory cells. Thus, the case shown in part (B) of FIG. 3 needs an interval of 12 clocks from the write command W to the read command R. Thus, in the case shown in part (B) of FIG. 3, the read-write cycle which is the interval between the read command R and the write command W is equal to 16 clocks.
As described above, the sequence of alternately performing the read operation and the write operation is not as efficient as the sequence of successively performing the read or write operations.